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111
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HPCA
2012
IEEE
13 years 5 months ago
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads
Main memory latencies have always been a concern for system performance. Given that reads are on the critical path for CPU progress, reads must be prioritized over writes. However...
Niladrish Chatterjee, Naveen Muralimanohar, Rajeev...
75
Voted
ISCA
2009
IEEE
148views Hardware» more  ISCA 2009»
15 years 4 months ago
Disaggregated memory for expansion and sharing in blade servers
Analysis of technology and application trends reveals a growing imbalance in the peak compute-to-memory-capacity ratio for future servers. At the same time, the fraction contribut...
Kevin T. Lim, Jichuan Chang, Trevor N. Mudge, Part...
FPL
2003
Springer
120views Hardware» more  FPL 2003»
15 years 2 months ago
Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms
The power-efficient implementation of motion estimation algorithms on a system comprised by an FPGA and an external memory is presented. Low power consumption is achieved by implem...
Konstantinos Tatas, K. Siozios, Dimitrios Soudris,...
HICSS
1999
IEEE
112views Biometrics» more  HICSS 1999»
15 years 1 months ago
Defining Uniform and Hybrid Memory Consistency Models on a Unified Framework
The behavior of Distributed Shared Memory Systems is dictated by the Memory Consistency Model. Several Memory Consistency Models have been proposed in the literature and they fit ...
Alba Cristina Magalhaes Alves de Melo
ARCS
2008
Springer
14 years 11 months ago
Self-aware Memory: Managing Distributed Memory in an Autonomous Multi-master Environment
Abstract. A major problem considering parallel computing is maintaining memory consistency and coherency, and ensuring ownership and access rights. These problems mainly arise from...
Rainer Buchty, Oliver Mattes, Wolfgang Karl