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ASPLOS
1996
ACM
15 years 9 months ago
Synchronization and Communication in the T3E Multiprocessor
This paper describes the synchronization and communication primitives of the Cray T3E multiprocessor, a shared memory system scalable to 2048 processors. We discuss what we have l...
Steven L. Scott
ICCAD
1994
IEEE
105views Hardware» more  ICCAD 1994»
15 years 9 months ago
Register assignment through resource classification for ASIP microcode generation
Application Specific Instruction-Set Processors (ASIPs) offer designers the ability for high-speed data and control processing with the added flexibility needed for late design sp...
Clifford Liem, Trevor C. May, Pierre G. Paulin
CTRSA
2006
Springer
146views Cryptology» more  CTRSA 2006»
15 years 8 months ago
Cache Attacks and Countermeasures: The Case of AES
We describe several software side-channel attacks based on inter-process leakage through the state of the CPU's memory cache. This leakage reveals memory access patterns, whic...
Dag Arne Osvik, Adi Shamir, Eran Tromer
ISHPC
2000
Springer
15 years 8 months ago
The New DRAM Interfaces: SDRAM, RDRAM and Variants
For the past two decades, developments in DRAM technology, the primary technology for the main memory of computers, have been directed towards increasing density. As a result 256 M...
Brian Davis, Bruce L. Jacob, Trevor N. Mudge
182
Voted
EDBT
1992
ACM
111views Database» more  EDBT 1992»
15 years 8 months ago
Pipelined Query Processing in the DBGraph Storage Model
The DBGraph storage model, designed for main memory DBMS, ensures both data storage compactness and efficient processing for all database operations. By representing the entire da...
Philippe Pucheral, Jean-Marc Thévenin