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SIGMETRICS
2011
ACM
198views Hardware» more  SIGMETRICS 2011»
14 years 10 months ago
Memory Trace Compression and Replay for SPMD Systems using Extended PRSDs?
Concurrency levels in large-scale supercomputers are rising exponentially, and shared-memory nodes with hundreds of cores and non-uniform memory access latencies are expected with...
Sandeep Budanur, Frank Mueller, Todd Gamblin
GLVLSI
2008
IEEE
169views VLSI» more  GLVLSI 2008»
15 years 3 months ago
Simultaneous optimization of memory configuration and code allocation for low power embedded systems
This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low Vdd and Vth and 2) a static power ...
Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura
DATE
1999
IEEE
113views Hardware» more  DATE 1999»
15 years 7 months ago
Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems
This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed m...
William Fornaciari, Donatella Sciuto, Cristina Sil...
ASPLOS
2010
ACM
15 years 9 months ago
Specifying and dynamically verifying address translation-aware memory consistency
Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation (AT) systems. Detecting bugs and faults requires a clear speciï...
Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. So...
PLILP
1993
Springer
15 years 7 months ago
An OR Parallel Prolog Model for Distributed Memory Systems
This paper shows a multisequential model to exploit OR parallelism on distributed memory systems. It presents an implementation of the incremental copy mechanism oriented to distr...
Vicente Benjumea, José M. Troya