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ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
15 years 8 months ago
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays
Microprocessor clock frequency has improved by nearly 40% annually over the past decade. This improvement has been provided, in equal measure, by smaller technologies and deeper p...
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler,...
159
Voted
ICECCS
1998
IEEE
123views Hardware» more  ICECCS 1998»
15 years 7 months ago
Applying Slicing Technique to Software Architectures
Software architecture is receiving increasingly attention as a critical design level for software systems. As software architecture design resources (in the form of architectural ...
Jianjun Zhao
129
Voted
INFOCOM
1999
IEEE
15 years 8 months ago
User-Friendly Access Control for Public Network Ports
We are facing a growing user demand for ubiquitous Internet access. As a result, network ports and wireless LANs are becoming common in public spaces inside buildings such as loung...
Guido Appenzeller, Mema Roussopoulos, Mary Baker
119
Voted
JSAC
2008
167views more  JSAC 2008»
15 years 3 months ago
DTN: an architectural retrospective
We review the rationale behind the current design of the Delay/Disruption Tolerant Networking (DTN) Architecture and highlight some remaining open issues. Its evolution, from a foc...
Kevin R. Fall, Stephen Farrell
122
Voted
ASPLOS
2010
ACM
15 years 7 months ago
Orthrus: efficient software integrity protection on multi-cores
This paper proposes an efficient hardware/software system that significantly enhances software security through diversified replication on multi-cores. Recent studies show that a ...
Ruirui Huang, Daniel Y. Deng, G. Edward Suh