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FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
15 years 6 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
CGO
2010
IEEE
15 years 4 months ago
Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bi
For memory constrained embedded systems code size is at least as important as performance. One way of increasing code density is to exploit compact instruction formats, e.g. ARM T...
Tobias J. K. Edler von Koch, Igor Böhm, Bj&ou...
67
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WWW
2010
ACM
15 years 4 months ago
New-web search with microblog annotations
Web search engines discover indexable documents by recursively ‘crawling’ from a seed URL. Their rankings take into account link popularity. While this works well, it introduc...
Tom Rowlands, David Hawking, Ramesh Sankaranarayan...
LCTRTS
2010
Springer
15 years 4 months ago
Operation and data mapping for CGRAs with multi-bank memory
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and movi...
Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunh...
FPGA
2009
ACM
159views FPGA» more  FPGA 2009»
15 years 4 months ago
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the inte...
Raphael Rubin, André DeHon