Sciweavers

109 search results - page 6 / 22
» Simplifying Instruction Issue Logic in Superscalar Processor...
Sort
View
ISSS
1998
IEEE
120views Hardware» more  ISSS 1998»
15 years 1 months ago
Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Allocation
Designing a cost effective superscalar architecture for x86 compatible microprocessors is a challenging task in terms of both technical difficulty and commercial value. One of the...
Ing-Jer Huang, Ping-Huei Xie
DAC
1996
ACM
15 years 1 months ago
Techniques for Verifying Superscalar Microprocessors
Burch and Dill [3] described an automatic method for verifying a pipelined processor against its instruction setarchitecture(ISA). We describethree techniquesfor improving this me...
Jerry R. Burch
ARCS
2010
Springer
15 years 4 months ago
How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT
This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-ti...
Jörg Mische, Irakli Guliashvili, Sascha Uhrig...
MICRO
1997
IEEE
93views Hardware» more  MICRO 1997»
15 years 1 months ago
A Comparison of Data Prefetching on an Access Decoupled and Superscalar Machine
In this paper we investigate the behavior of data prefetching on an access decoupled machine and a superscalar machine. We assess if there are bene ts to using the decoupling para...
G. P. Jones, Nigel P. Topham
MICRO
1998
IEEE
108views Hardware» more  MICRO 1998»
15 years 1 months ago
Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications
Three dimensional (3D) graphics applications have become very important workloads running on today's computer systems. A cost-effective graphics solution is to perform geomet...
Chia-Lin Yang, Barton Sano, Alvin R. Lebeck