41 search results - page 5 / 9 » Simulated Annealing Based Temperature Aware Floorplanning |
ASPDAC
2005
ACM
15 years 3 months ago
2005
ACM
— The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wirelength. However, wire congestion and thermal issues are exacerbated d...
TPDS
2010
14 years 7 months ago
2010
Abstract—A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, highspeed interface to increase the device den...
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
— Fixed-die floorplanning is an important problem in the modern physical design process. An effective floorplanning algorithm is crucial to improving both the quality and the t...
ICCTA
2007
IEEE
15 years 1 months ago
2007
IEEE
In this paper, we propose a placement method for islandstyle FPGAs, based on fast yet very good initial placement followed by refinement using ultra-low temperature Simulated Anne...
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ISCA
2003
IEEE
15 years 2 months ago
2003
IEEE
With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processo...