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ASPDAC
2000
ACM
111views Hardware» more  ASPDAC 2000»
15 years 6 months ago
Gate-level aged timing simulation methodology for hot-carrier reliability assurance
- This paper presents a new aged timing simulation methodology that can be used for hot-carrier reliability assurance of VLSI. This methodology consists of a compact model and a un...
Yoshiyuki Kawakami, Jingkun Fang, Hirokazu Yonezaw...
103
Voted
RTCSA
1999
IEEE
15 years 6 months ago
Pipeline Timing Analysis Using a Trace-Driven Simulator
In this paper we present a technique for Worst-Case Execution Time WCET analysis for pipelined processors. Our technique uses a standard simulator instead of special-purpose pipel...
Jakob Engblom, Andreas Ermedahl
WSC
2008
15 years 4 months ago
Maximizing the utilization of operating rooms with stochastic times using simulation
This paper addresses a surgery rooms scheduling problem. The problem is modeled as a parallel machine scheduling problem with sequence dependent setup times and an objective of mi...
Jean-Paul M. Arnaout, Sevag Kulbashian
DSRT
2005
IEEE
15 years 7 months ago
A MDA-based approach for real time embedded systems simulation
This document presents a simulation-based method for the development of real time embedded systems. This kind of system is really sensitive to the communication with external envi...
Julien DeAntoni, Jean-Philippe Babau
WSC
2007
15 years 4 months ago
Measuring manufacturing throughput using takt time analysis and simulation
This paper is motivated by a case study performed at a company that manufactures two main types of customized products. In an effort to significantly increase their throughput cap...
Jun Duanmu, Kevin Taaffe