Abstract—Continuously shrinking feature sizes cause an increasing vulnerability of digital circuits. Manufacturing failures and transient faults may tamper the functionality. Aut...
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
In this paper we present a concept and an architecture for a location dependent Digital Rights Management system. The solution is based on a trusted hardware which incorporates th...
On initiative of the Commission of the European Communities, the Information Technology Security Evaluation Criteria (ITSEC) are designed to provide a yardstick for the evaluation...
—This paper proposes a general scheduling model that extends job-shop scheduling models to incorporate important features of real manufacturing systems. More precisely, each oper...