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SIMPRA
2008
137views more  SIMPRA 2008»
15 years 2 months ago
An admissible-behaviour-based analysis of the deadlock in Petri-net controllers
This paper addresses the problem of verifying the discrete control logic that is typically implemented by programmable controllers. Not only are the logical properties of the cont...
G. Music, Drago Matko
GLVLSI
2005
IEEE
104views VLSI» more  GLVLSI 2005»
15 years 9 months ago
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing
The ever-increasing number of transistors on a chip has resulted in very large scale integration (VLSI) systems whose performance and manufacturing costs are driven by on-chip wir...
Ajay Joshi, Jeffrey A. Davis
231
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FDL
2004
IEEE
15 years 7 months ago
Real-Time Operating System Services for Realistic SystemC Simulation Models of Embedded Systems
gn process of embedded systems moves currently towards higher levels of abstraction. As a consequence, a need arises for an early and realistic assessment of system level design d...
P. Hastono, Stephan Klaus, Sorin A. Huss
VLSID
2002
IEEE
94views VLSI» more  VLSID 2002»
16 years 3 months ago
Timing Yield Calculation Using an Impulse-Train Approach
This paper presents a new method to compute the probability distribution of the delay of a combinational circuit and uses it obtain an estimate of the yield of the process that ma...
Srinath R. Naidu
ITC
2002
IEEE
102views Hardware» more  ITC 2002»
15 years 8 months ago
Fault Grading FPGA Interconnect Test Configurations
Conventional fault simulation techniques for FPGAs are very complicated and time consuming. The other alternative, FPGA fault emulation technique, is incomplete, and can be used o...
Mehdi Baradaran Tahoori, Subhasish Mitra, Shahin T...