1304 search results - page 37 / 261 » Simulation of Soliton Circuits |
QEST
2010
IEEE
14 years 7 months ago
2010
IEEE
Traditional architecture design approaches hide hardware uncertainties from the software stack through overdesign, which is often expensive in terms of power consumption. The recen...
ASYNC
2010
IEEE
14 years 1 months ago
2010
IEEE
— Synchronizers play a key role in multi-clock domain systems on chip. Traditionally, improvement of synchronization parameters with scaling has been assumed. In particular, the ...
ISCAS
2003
IEEE
15 years 3 months ago
2003
IEEE
A closed form expression for the rise time of a gate driving a distributed RLC line is introduced that is within 8% of dynamic circuit simulations for a wide range of RLC loads. I...
VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
DAC
2009
ACM
15 years 4 months ago
2009
ACM
This paper proposes an equation-based multi-scenario iterative robust optimization methodology for analog/mixed-signal circuits. We show that due to local circuit performance mono...