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ISCAS
2006
IEEE
93views Hardware» more  ISCAS 2006»
15 years 4 months ago
A low-power clock frequency multiplier
A low-power output feedback controlled frequency synthesizer. Our proposed circuit can be used for low-power multiplier is proposed for Delay Locked Loop (DLL) based application an...
Md. Ibrahim Faisal, Magdy A. Bayoumi, Peiyi Zhao
HPCA
2012
IEEE
13 years 5 months ago
Flexible register management using reference counting
Conventional out-of-order processors that use a unified physical register file allocate and reclaim registers explicitly using a free list that operates as a circular queue. We ...
Steven Battle, Andrew D. Hilton, Mark Hempstead, A...
DELTA
2002
IEEE
15 years 2 months ago
Multi-Level Fault Simulation of Digital Systems on Decision Diagrams
A new method for hierarchical fault simulation based on multi-level Decision Diagrams (DD) is proposed. We suppose that a register transfer (RT) level information along with gate-...
Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik
DDECS
2006
IEEE
106views Hardware» more  DDECS 2006»
15 years 4 months ago
Dynamic Decimal Adder Circuit Design by using the Carry Lookahead
- This paper presents a carry lookahead (CLA) circuitry design based on dynamic circuit aiming at delay reduction in addition of BCD coded decimal numbers. The performance of the p...
Younggap You, Yong-Dae Kim, Jong Hwa Choi
ISCAS
2005
IEEE
192views Hardware» more  ISCAS 2005»
15 years 3 months ago
A sub-1V bandgap reference circuit using subthreshold current
— A bandgap reference circuit employing subthreshold current is proposed. Only a small fraction of VBE is utilized to generate the reference voltage of 170mV. Since the subthresh...
Hongchin Lin, Chao-Jui Liang