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VTS
2006
IEEE
101views Hardware» more  VTS 2006»
15 years 4 months ago
Design Optimization for Robustness to Single Event Upsets
Abstract: An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU...
Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
ECAL
2005
Springer
15 years 3 months ago
Ant-Based Computing
We propose a biologically and physically plausible model for ants and pheromones, and show this model to be sufficiently powerful to simulate the computation of arbitrary logic cir...
Loizos Michael
ISCAS
2003
IEEE
124views Hardware» more  ISCAS 2003»
15 years 3 months ago
Analysis of output ripple in multi-phase clocked charge pumps
This paper presents a mathematical analysis of the ripple voltage caused by a mismatch in parasitic capacitances in multi-phase, clocked charge pumps. Through detailed circuit mod...
Louie Pylarinos, Khoman Phang
EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
15 years 1 months ago
Quality considerations in delay fault testing
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...
Alicja Pierzynska, Slawomir Pilarski
ENGL
2007
118views more  ENGL 2007»
14 years 10 months ago
Design of Low Power CMOS Crystal Oscillator with Tuning Capacitors
—A low power CMOS crystal oscillator was proposed with high accuracy by tuning capacitors. Based on the analysis concerning power consumption, start-up time, and frequency stabil...
Shun Yao, Hengfang Zhu, Xiaobo Wu