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» Simulation of Soliton Circuits
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DATE
2003
IEEE
108views Hardware» more  DATE 2003»
15 years 3 months ago
Generalized Posynomial Performance Modeling
This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. The coefficient set ...
Tom Eeckelaert, Walter Daems, Georges G. E. Gielen...
ARVLSI
2001
IEEE
305views VLSI» more  ARVLSI 2001»
15 years 1 months ago
Logic Design Considerations for 0.5-Volt CMOS
As the operating supply voltage for commercial CMOS devices falls below 2 V, research activities are underway to develop CMOS integrated circuits that can operate at supply voltag...
K. Joseph Hass, Jack Venbrux, Prakash Bhatia
ASPDAC
2001
ACM
75views Hardware» more  ASPDAC 2001»
15 years 1 months ago
Correlation method of circuit-performance and technology fluctuations for improved design reliability
Abstract-- We propose a method of correlating circuit performance with technology fluctuations during the circuit-design phase. The method employs test circuits sensitive for techn...
D. Miyawaki, Shizunori Matsumoto, Hans Jürgen...
TIM
2010
294views Education» more  TIM 2010»
14 years 4 months ago
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
HeungJun Jeon, Yong-Bin Kim, Minsu Choi
ICCD
2007
IEEE
190views Hardware» more  ICCD 2007»
15 years 7 months ago
Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits
Hybrid nanoelectronics are emerging as one viable option to sustain the Moore’s Law after the CMOS scaling limit is reached. One main design challenge in hybrid nanoelectronics ...
Shu Li, Tong Zhang