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GLVLSI
2007
IEEE
15 years 3 months ago
2007
IEEE
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
In this paper, a novel design space exploration approach is proposed that enables a concurrent optimization of the topology, the process binding, and the communication routing of ...
TCAD
2010
14 years 4 months ago
2010
Crosstalk faults have emerged as a significant mechanism for circuit failure. Long signal nets are of particular concern because they tend to have a higher coupling capacitance to...
DAC
2012
ACM
12 years 12 months ago
2012
ACM
In this paper, we propose two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack. First, TSVs are spread on each die to reduce t...
DAC
2007
ACM
15 years 10 months ago
2007
ACM
In this paper, we propose TROY, the first track router with yield-driven wire planning to optimize yield loss due to random defects. As the probability of failure (POF) computed f...