9 search results - page 1 / 2 » Simultaneous test pattern compaction, ordering and X-filling... |
ISQED
2009
IEEE
15 years 6 months ago
2009
IEEE
90
Voted
DATE
2008
IEEE
15 years 6 months ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
DAC
2008
ACM
16 years 19 days ago
2008
ACM
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
106
Voted
DAC
2003
ACM
15 years 4 months ago
2003
ACM
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
86
Voted
DATE
2008
IEEE
15 years 6 months ago
2008
IEEE
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...