719 search results - page 17 / 144 » Sizing router buffers |
85
Voted
ASPDAC
2005
ACM
15 years 2 months ago
2005
ACM
Incremental physical design is an important methodology towards achieving design closure for high-performance large-scale circuits. Placement tools must accommodate incremental ch...
104
Voted
ICCAD
2008
IEEE
15 years 9 months ago
2008
IEEE
— VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated...
80
Voted
ISLPED
1996
ACM
15 years 4 months ago
1996
ACM
In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions...
ISPD
1997
ACM
15 years 4 months ago
1997
ACM
In this paper, we consider the delay minimization problem of a wire by simultaneously considering bu er insertion, bu er sizing and wire sizing. We consider three versions of the ...
124
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DAC
2006
ACM
15 years 6 months ago
2006
ACM
This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequent...