719 search results - page 54 / 144 » Sizing router buffers |
114
click to vote
ENTCS
2008
15 years 18 days ago
2008
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficient...
115
Voted
FPGA
2000
ACM
15 years 4 months ago
2000
ACM
In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cl...
94
Voted
ICNP
1996
IEEE
15 years 4 months ago
1996
IEEE
Recent measurements of local-area and wide-area traffic have shown that network traffic exhibits variability at a wide range of scales. In this paper, we examine a mechanism that ...
97
Voted
ICCAD
2003
IEEE
15 years 9 months ago
2003
IEEE
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible...
101
Voted
VTS
2008
IEEE
15 years 7 months ago
2008
IEEE
Trace buffers are commonly used to capture data during in-system silicon debug. This paper exploits the fact that it is not necessary to capture error-free data in the trace buffe...