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SBCCI
2004
ACM
117views VLSI» more  SBCCI 2004»
15 years 3 months ago
Reducing test time with processor reuse in network-on-chip based systems
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
Alexandre M. Amory, Érika F. Cota, Marcelo ...
ISCA
2012
IEEE
320views Hardware» more  ISCA 2012»
13 years 6 days ago
Viper: Virtual pipelines for enhanced reliability
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...
Andrea Pellegrini, Joseph L. Greathouse, Valeria B...
FPGA
2005
ACM
105views FPGA» more  FPGA 2005»
15 years 3 months ago
Soft error rate estimation and mitigation for SRAM-based FPGAs
FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tole...
Ghazanfar Asadi, Mehdi Baradaran Tahoori
ICCD
2003
IEEE
113views Hardware» more  ICCD 2003»
15 years 6 months ago
Exploiting Microarchitectural Redundancy For Defect Tolerance
Continued advancements in fabrication technology and reductions in feature size create challenges in maintaining both manufacturing yield rates and long-term reliability of device...
Premkishore Shivakumar, Stephen W. Keckler, Charle...
PVLDB
2008
103views more  PVLDB 2008»
14 years 9 months ago
A request-routing framework for SOA-based enterprise computing
Enterprises may use a service-oriented architecture (SOA) to provide a streamlined interface to their business processes. To scale up the system, each tier in a composite service ...
Thomas Phan, Wen-Syan Li