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DFT
2006
IEEE
203views VLSI» more  DFT 2006»
14 years 15 days ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
DATE
2007
IEEE
143views Hardware» more  DATE 2007»
14 years 23 days ago
Portable multimedia SoC design: a global challenge
- The intrinsic capability brought by each new technology node opens the way to a broad range of system integration options and continuously enables new applications to be integrat...
Maurizio Paganini, Georg Kimmich, Stephane Ducrey,...
ASPDAC
2008
ACM
103views Hardware» more  ASPDAC 2008»
13 years 8 months ago
Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification
This paper presents an all digital measurement circuit called "gated oscillator" for capturing waveforms of dynamic power supply noise. The gated oscillator is constructe...
Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoy...
ICCAD
2009
IEEE
94views Hardware» more  ICCAD 2009»
13 years 4 months ago
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...
Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. ...
ISVLSI
2007
IEEE
181views VLSI» more  ISVLSI 2007»
14 years 21 days ago
Code-coverage Based Test Vector Generation for SystemC Designs
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
Alair Dias Jr., Diógenes Cecilio da Silva J...