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» Software Cache Coherence for Large Scale Multiprocessors
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HPCA
2009
IEEE
14 years 6 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
ASPLOS
2006
ACM
14 years 7 days ago
AVIO: detecting atomicity violations via access interleaving invariants
Concurrency bugs are among the most difficult to test and diagnose of all software bugs. The multicore technology trend worsens this problem. Most previous concurrency bug detect...
Shan Lu, Joseph Tucek, Feng Qin, Yuanyuan Zhou
SPAA
2006
ACM
14 years 6 days ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
EMSOFT
2005
Springer
13 years 11 months ago
High-level real-time programming in Java
Real-time systems have reached a level of complexity beyond the scaling capability of the low-level or restricted languages traditionally used for real-time programming. While Met...
David F. Bacon, Perry Cheng, David Grove, Michael ...
SIGGRAPH
1998
ACM
13 years 10 months ago
The Clipmap: A Virtual Mipmap
We describe the clipmap, a dynamic texture representation that efficiently caches textures of arbitrarily large size in a finite amount of physical memory for rendering at real-...
Christopher C. Tanner, Christopher J. Migdal, Mich...