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SLIP
2009
ACM
15 years 8 months ago
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim
ICPP
2000
IEEE
15 years 6 months ago
Multilayer VLSI Layout for Interconnection Networks
Current VLSI technology allows more than two wiring layers and the number is expected to rise in future. In this paper, we show that, by designing VLSI layouts directly for an L-l...
Chi-Hsiang Yeh, Emmanouel A. Varvarigos, Behrooz P...
CORR
2010
Springer
151views Education» more  CORR 2010»
15 years 5 days ago
Adding a referee to an interconnection network: What can(not) be computed in one round
Abstract—In this paper we ask which properties of a distributed network can be computed from a few amount of local information provided by its nodes. The distributed model we con...
Florent Becker, Martín Matamala, Nicolas Ni...
FMCO
2004
Springer
112views Formal Methods» more  FMCO 2004»
15 years 7 months ago
Probabilistic Linda-Based Coordination Languages
Abstract. Coordination languages are intended to simplify the development of complex software systems by separating the coordination aspects of an application from its computation ...
Alessandra Di Pierro, Chris Hankin, Herbert Wiklic...
CAISE
2003
Springer
15 years 6 months ago
A Framework for the Design of ETL Scenarios
Extraction-Transformation-Loading (ETL) tools are pieces of software responsible for the extraction of data from several sources, their cleansing, customization and insertion into ...
Panos Vassiliadis, Alkis Simitsis, Panos Georganta...