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ISQED
2002
IEEE
126views Hardware» more  ISQED 2002»
15 years 6 months ago
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-...
ICCAD
2003
IEEE
123views Hardware» more  ICCAD 2003»
15 years 10 months ago
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Io...
TVLSI
2010
14 years 8 months ago
Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling
To efficiently analyze the large-scale interconnect dominant circuits with inductive couplings (mutual inductances), this paper introduces a new state matrix, called VNA, to stamp ...
Hao Yu, Chunta Chu, Yiyu Shi, David Smart, Lei He,...
IPPS
2007
IEEE
15 years 8 months ago
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
Ehsan Atoofian, Amirali Baniasadi
IPPS
2007
IEEE
15 years 8 months ago
Low-Overhead LogGP Parameter Assessment for Modern Interconnection Networks
Network performance measurement and prediction is very important to predict the running time of high performance computing applications. The LogP model family has been proven to b...
Torsten Hoefler, Andre Lichei, Wolfgang Rehm