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DATE
2007
IEEE
174views Hardware» more  DATE 2007»
16 years 1 months ago
ATLAS: a chip-multiprocessor with transactional memory support
Chip-multiprocessors are quickly becoming popular in embedded systems. However, the practical success of CMPs strongly depends on addressing the difficulty of multithreaded appli...
Njuguna Njoroge, Jared Casper, Sewook Wee, Yuriy T...
DATE
2007
IEEE
103views Hardware» more  DATE 2007»
16 years 1 months ago
Flexible hardware reduction for elliptic curve cryptography in GF(2m)
In this paper we discuss two ways to provide flexible hardware support for the reduction step in Elliptic Curve Cryptography in binary fields (GF(2m )). In our first approach w...
Steffen Peter, Peter Langendörfer, Krzysztof ...
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
16 years 1 months ago
Two-level microprocessor-accelerator partitioning
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...
GLVLSI
2007
IEEE
189views VLSI» more  GLVLSI 2007»
16 years 1 months ago
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...
HPDC
2007
IEEE
16 years 1 months ago
Feedback-directed thread scheduling with memory considerations
This paper describes a novel approach to generate an optimized schedule to run threads on distributed shared memory (DSM) systems. The approach relies upon a binary instrumentatio...
Fengguang Song, Shirley Moore, Jack Dongarra
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