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IPPS
2006
IEEE
15 years 3 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
53
Voted
VTC
2006
IEEE
102views Communications» more  VTC 2006»
15 years 3 months ago
Backward Compatible Modulation Schemes for Improving Spectrum Efficiency in DAB Systems
In this study, a new physical layer transmission technique is proposed with the spectrum efficiency up to two times of that of the Eureka-147 DAB system. The proposed technique com...
Chih-Yang Kao, Ming-Chien Tseng, Ching-Yung Chen, ...
85
Voted
IEEECIT
2010
IEEE
14 years 8 months ago
Introducing Hardware-in-Loop Concept to the Hardware/Software Co-design of Real-time Embedded Systems
—As the need for embedded systems to interact with other systems is growing fast, we see great opportunities in introducing the hardware-in-the-loop technique to the field of ha...
Dogan Fennibay, Arda Yurdakul, Alper Sen
GECCO
2006
Springer
210views Optimization» more  GECCO 2006»
15 years 1 months ago
Clustering the heap in multi-threaded applications for improved garbage collection
Garbage collection can be a performance bottleneck in large distributed, multi-threaded applications. Applications may produce millions of objects during their lifetimes and may i...
Myra B. Cohen, Shiu Beng Kooi, Witawas Srisa-an
EUROCRYPT
2011
Springer
14 years 1 months ago
Faster Explicit Formulas for Computing Pairings over Ordinary Curves
Abstract. We describe efficient formulas for computing pairings on ordinary elliptic curves over prime fields. First, we generalize lazy reduction techniques, previously considere...
Diego F. Aranha, Koray Karabina, Patrick Longa, Ca...