744 search results - page 64 / 149 » Software Transactional Memory on Relaxed Memory Models |
138
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ISPASS
2003
IEEE
15 years 9 months ago
2003
IEEE
Abstract— This paper proposes to speedup sampled microprocessor simulations by reducing warmup times without sacrificing simulation accuracy. It exploiting the observation that ...
127
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IPPS
2000
IEEE
15 years 8 months ago
2000
IEEE
As the speed gap between CPU and memory widens, memory hierarchy has become the primary factor limiting program performance. Until now, the principal focus of hardware and softwar...
126
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ISPASS
2007
IEEE
15 years 10 months ago
2007
IEEE
This paper proposes the use of microprocessor performance counters for online measurement of complete system power consumption. While past studies have demonstrated the use of per...
123
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IPPS
2007
IEEE
15 years 10 months ago
2007
IEEE
OpenMP has emerged as an important model and language extension for shared-memory parallel programming. On shared-memory platforms, OpenMP offers an intuitive, incremental approac...
141
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IPPS
2002
IEEE
15 years 8 months ago
2002
IEEE
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...