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CGO
2009
IEEE
15 years 11 months ago
Computer Generation of General Size Linear Transform Libraries
The development of high-performance libraries has become extraordinarily difficult due to multiple processor cores, vector instruction sets, and deep memory hierarchies. Often, t...
Yevgen Voronenko, Frédéric de Mesmay...
ASAP
2007
IEEE
123views Hardware» more  ASAP 2007»
15 years 11 months ago
A memcpy Hardware Accelerator Solution for Non Cache-line Aligned Copies
In this paper, we present a hardware solution to perform non cache-line aligned memory copies allowing the commonly used memcpy function to cope with word copies. The main purpose...
Filipa Duarte, Stephan Wong
CASES
2001
ACM
15 years 8 months ago
Energy-efficient instruction cache using page-based placement
Energy consumption is a crucial factor in designing batteryoperated embedded and mobile systems. The memory system is a major contributor to the system energy in such environments...
Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. K...
IWMM
2009
Springer
107views Hardware» more  IWMM 2009»
15 years 11 months ago
Self-recovery in server programs
It is important that long running server programs retain availability amidst software failures. However, server programs do fail and one of the important causes of failures in ser...
Vijay Nagarajan, Dennis Jeffrey, Rajiv Gupta
CF
2010
ACM
15 years 9 months ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...