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CODES
2011
IEEE
14 years 3 months ago
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
Garo Bournoutian, Alex Orailoglu
CHES
2004
Springer
128views Cryptology» more  CHES 2004»
15 years 9 months ago
Long Modular Multiplication for Cryptographic Applications
Abstract. A digit-serial, multiplier-accumulator based cryptographic coprocessor architecture is proposed, similar to fix-point DSP's with enhancements, supporting long modula...
Laszlo Hars
CSFW
2010
IEEE
15 years 8 months ago
On Protection by Layout Randomization
Abstract—Layout randomization is a powerful, popular technique for software protection. We present it and study it in programming-language terms. More specifically, we consider ...
Martín Abadi, Gordon D. Plotkin
JUCS
2007
122views more  JUCS 2007»
15 years 3 months ago
A New Architecture for Concurrent Lazy Cyclic Reference Counting on Multi-Processor Systems
: Multi-processor systems have become the standard in current computer architectures. Software developers have the possibility to take advantage of the additional computing power a...
Andrei de Araújo Formiga, Rafael Dueire Lin...
MOC
2010
14 years 10 months ago
Optimizing the double description method for normal surface enumeration
Abstract. Many key algorithms in 3-manifold topology involve the enumeration of normal surfaces, which is based upon the double description method for finding the vertices of a con...
Benjamin A. Burton