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CODES
2006
IEEE
15 years 7 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
113
Voted
SSR
2001
73views more  SSR 2001»
15 years 3 months ago
XML implementation of frame processor
A quantitative study has shown that frame technology [1] supported by Fusion toolset can lead to reduction in time-tomarket (70%) and project costs (84%). Frame technology has bee...
Tak Wong, Stan Jarzabek, Soe Myat Swe, Ru Shen, Ho...
EUROSYS
2006
ACM
15 years 11 months ago
Using queries for distributed monitoring and forensics
Distributed systems are hard to build, profile, debug, and test. Monitoring a distributed system – to detect and analyze bugs, test for regressions, identify fault-tolerance pr...
Atul Singh, Petros Maniatis, Timothy Roscoe, Peter...
CODES
2008
IEEE
15 years 8 months ago
Intra- and inter-processor hybrid performance modeling for MPSoC architectures
The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid perfor...
Frank E. B. Ophelders, Samarjit Chakraborty, Henk ...
LCTRTS
2005
Springer
15 years 7 months ago
Syncopation: generational real-time garbage collection in the metronome
Real-time garbage collection has been shown to be feasible, but for programs with high allocation rates, the utilization achievable is not sufficient for some systems. Since a hi...
David F. Bacon, Perry Cheng, David Grove, Martin T...