1942 search results - page 39 / 389 » Speeding Up XTR |
ERSA
2003
15 years 1 months ago
2003
The availability of SiGe HBT devices has opened a door for Gigahertz FPGAs. However, the large device power consumption limits its scale. In order to solve this problem, a Multipl...
ISCAS
2007
IEEE
15 years 6 months ago
2007
IEEE
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
HIPEAC
2005
Springer
15 years 5 months ago
2005
Springer
Abstract. While cycle-accurate simulation tools have been widely used in modeling high-performance processors, such an approach can be hindered by the increasing complexity of the ...
ICCV
2009
IEEE
16 years 4 months ago
2009
IEEE
Prominent feature point descriptors such as SIFT and
SURF allow reliable real-time matching but at a compu-
tational cost that limits the number of points that can be
handled on...
MASCOTS
2004
15 years 1 months ago
2004
This paper describes the design and implementation of our high speed simulator for out-of-order microprocessors named BurstScalar. The simulator is based on the wellknown SimpleSc...