3693 search results - page 462 / 739 » Splitting a Logic Program |
207
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SIGMOD
2008
ACM
16 years 3 months ago
2008
ACM
We present a novel design and implementation of relational join algorithms for new-generation graphics processing units (GPUs). The most recent GPU features include support for wr...
113
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ICCAD
2007
IEEE
2007
IEEE
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
16 years 12 days ago
—Register allocation, in high-level synthesis and ASIP design, is the process of determining the number of registers to include in the resulting circuit or processor. The goal is...
115
Voted
CGO
2010
IEEE
15 years 10 months ago
2010
IEEE
Decoupled Software Pipelining (DSWP) is one approach to automatically extract threads from loops. It partitions loops into long-running threads that communicate in a pipelined man...
137
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CEC
2008
IEEE
15 years 10 months ago
2008
IEEE
—Genetic programming (GP), is a very general and efficient technique, often capable of outperforming more specialized techniques on a variety of tasks. In this paper, we suggest ...
131
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CCGRID
2007
IEEE
15 years 9 months ago
2007
IEEE
Malleability enables a parallel application’s execution system to split or merge processes modifying granularity. While process migration is widely used to adapt applications to...