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» State machine models of timing and circuit design
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CASES
2007
ACM
15 years 2 months ago
Cache leakage control mechanism for hard real-time systems
Leakage energy consumption is an increasingly important issue as the technology continues to shrink. Since on-chip caches constitute a major portion of the processor's transi...
Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia...
ATS
2003
IEEE
131views Hardware» more  ATS 2003»
15 years 3 months ago
Software-Based Delay Fault Testing of Processor Cores
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hi...
MEMOCODE
2010
IEEE
14 years 7 months ago
Proving transaction and system-level properties of untimed SystemC TLM designs
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...
Daniel Große, Hoang M. Le, Rolf Drechsler
B
2007
Springer
15 years 4 months ago
Modelling and Proof Analysis of Interrupt Driven Scheduling
Following a brief discussion of uniprocessor scheduling in which we argue the case for formal analysis, we describe a distributed Event B model of interrupt driven scheduling. We ï...
Bill Stoddart, Dominique Cansell, Frank Zeyda
CDC
2009
IEEE
137views Control Systems» more  CDC 2009»
15 years 2 months ago
Generalized Model Predictive Direct Torque Control: Long prediction horizons and minimization of switching losses
Abstract— This paper presents a generalized Model Predictive Direct Torque Control scheme with an extended horizon, which is composed of multiple hinges (groups of switch transit...
Tobias Geyer