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» State machine models of timing and circuit design
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IJISTA
2007
124views more  IJISTA 2007»
14 years 9 months ago
Incremental learning for spoken affect classification and its application in call-centres
: This paper introduces a system for real-time incremental learning in a call-centre environment. The classifier used is a Support Vector Machine (SVM) and it is applied to telepho...
Donn Morrison, Ruili Wang, W. L. Xu, Liyanage C. D...
AINA
2010
IEEE
15 years 2 months ago
The Cost Effective Pre-processing Based NFA Pattern Matching Architecture for NIDS
—Network Intrusion Detection System (NIDS) is a system which can detect network attacks resulted from worms and viruses on the Internet. An efficient pattern matching algorithm p...
Yeim-Kuan Chang, Chen-Rong Chang, Cheng-Chien Su
JSA
2008
131views more  JSA 2008»
14 years 9 months ago
Formal verification of ASMs using MDGs
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...
Amjad Gawanmeh, Sofiène Tahar, Kirsten Wint...
DAC
2010
ACM
15 years 1 months ago
TSV stress aware timing analysis with applications to 3D-IC layout optimization
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee,...
CEC
2007
IEEE
14 years 11 months ago
Fitness inheritance in evolutionary and multi-objective high-level synthesis
Abstract—The high-level synthesis process allows the automatic design and implementation of digital circuits starting from a behavioral description. Evolutionary algorithms are v...
Christian Pilato, Gianluca Palermo, Antonino Tumeo...