1186 search results - page 162 / 238 » State machine models of timing and circuit design |
ICFP
2006
ACM
15 years 9 months ago
2006
ACM
The problem of expressing I/O and side effects in functional languages is a well-established one. This paper addresses this problem from a general semantic viewpoint by giving a u...
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ISCA
2012
IEEE
13 years 8 days ago
2012
IEEE
A significant portion of the energy dissipated in modern integrated circuits is consumed by the overhead associated with timing guardbands that ensure reliable execution. Timing ...
DAC
1998
ACM
15 years 10 months ago
1998
ACM
Dynamic power management schemes (also called policies) can be used to control the power consumption levels of electronic systems, by setting their components in different states,...
VLSID
2004
IEEE
15 years 10 months ago
2004
IEEE
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
DAC
1999
ACM
15 years 10 months ago
1999
ACM
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...