1186 search results - page 48 / 238 » State machine models of timing and circuit design |
TACAS
2007
Springer
15 years 3 months ago
2007
Springer
This paper presents a mechanised Hoare-style programming logic framework for assembly level programs. The framework has been designed to fit on top of operational semantics of rea...
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
In this paper, we present a reduced order inodeling methodology, based on the utilization of optimal non-uniform grids generated by Gaussian spectral rules, for the direct passive...
ISQED
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract — Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and sig...
ICCAD
1998
IEEE
15 years 2 months ago
1998
IEEE
Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is partic...
OOPSLA
2009
Springer
15 years 4 months ago
2009
Springer
Objects model the world, and state is fundamental to a faithful modeling. Engineers use state machines to understand and reason about state transitions, but programming languages ...