306 search results - page 26 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
107
Voted
DAC
1996
ACM
15 years 6 months ago
1996
ACM
In this paper, we outline general design steps of our synthesis tool to realize application specific co-processors such that for a given scientific application having intensive ite...
ICCD
2007
IEEE
15 years 10 months ago
2007
IEEE
We have developed a new statistical timing analysis approach that does not impose any assumptions on the nature of manufacturing variability and takes into account an arbitrary mo...
152
Voted
ASPDAC
2008
ACM
15 years 3 months ago
2008
ACM
In the nanometer manufacturing region, process variation causes significant uncertainty for circuit performance verification. Statistical static timing analysis (SSTA) is thus dev...
101
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FPL
2003
Springer
15 years 7 months ago
2003
Springer
Abstract. Data dependent circuits are logic circuits specialized to specific input data. They are smaller and faster than the original circuits, although they are not reusable and...
DAC
2008
ACM
16 years 2 months ago
2008
ACM
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...