306 search results - page 35 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
134
Voted
TON
2002
15 years 1 months ago
2002
Packet delay greatly influences the overall performance of network applications. It is therefore important to identify causes and location of delay performance degradation within ...
104
Voted
DATE
2002
IEEE
15 years 6 months ago
2002
IEEE
Advancing technology drives design technology and thus design automation EDA . How to model interconnect, how to handle degradation of signal integrity and increasing power densi...
COLING
2000
15 years 3 months ago
2000
Automatic transliteration problem is to transcribe foreign words in one's own alphabet. Machine generated transliteration can be useful in various applications such as indexi...
144
Voted
GLVLSI
2007
IEEE
15 years 5 months ago
2007
IEEE
he abstract and simple computation and communication mechanism in the synchronous computational model it is easy to simulate synchronous systems and to apply formal verification m...
137
Voted
CODES
2005
IEEE
15 years 7 months ago
2005
IEEE
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...