306 search results - page 37 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
106
click to vote
DFT
1998
IEEE
15 years 6 months ago
1998
IEEE
This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an ex...
161
Voted
ICFHR
2010
14 years 8 months ago
2010
The hierarchical nature of Chinese characters has inspired radical-based recognition, but radical segmentation from characters remains a challenge. We previously proposed a radica...
127
click to vote
POPL
2010
ACM
15 years 11 months ago
2010
ACM
The method of logical relations is a classic technique for proving the equivalence of higher-order programs that implement the same observable behavior but employ different intern...
142
Voted
ICCAD
1997
IEEE
15 years 5 months ago
1997
IEEE
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
140
Voted
GLVLSI
2010
IEEE
15 years 7 months ago
2010
IEEE
Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising directio...