306 search results - page 39 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
121
Voted
DAC
2006
ACM
16 years 2 months ago
2006
ACM
We propose a scalable and efficient parameterized block-based statistical static timing analysis algorithm incorporating both Gaussian and non-Gaussian parameter distributions, ca...
165
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CVIU
2011
14 years 5 months ago
2011
In this paper we combine methods from the field of computer vision with surface editing techniques to generate animated faces, which are all in full correspondence to each other....
142
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ICCAD
2003
IEEE
15 years 10 months ago
2003
IEEE
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
98
Voted
DAC
2003
ACM
16 years 2 months ago
2003
ACM
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal tra...
129
Voted
ASIAMS
2008
IEEE
15 years 8 months ago
2008
IEEE
A carry-select adder(CSA) can be implemented by using single ripple carry adder and an add-one circuit instead of using dual ripple-carry adders to reduce the area and power but w...