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» Statistical Modeling for Circuit Simulation
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WSC
2007
15 years 2 months ago
A simulation course for high school students
Computer simulation presents a variety of opportunities for high school students to receive exposure to mathematics and engineering in the real world. We describe in a highlevel w...
David Goldsman
VTS
2006
IEEE
101views Hardware» more  VTS 2006»
15 years 5 months ago
Design Optimization for Robustness to Single Event Upsets
Abstract: An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU...
Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
ICCD
1997
IEEE
123views Hardware» more  ICCD 1997»
15 years 4 months ago
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
John A. Chandy, Prithviraj Banerjee
DATE
2008
IEEE
204views Hardware» more  DATE 2008»
15 years 6 months ago
Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis
Shrinking feature sizes and process variations are of increasing concern in modern technology. It is urgent that we develop statistical interconnect timing models which are harmon...
Jun-Kuei Zeng, Chung-Ping Chen
ICCAD
2006
IEEE
100views Hardware» more  ICCAD 2006»
15 years 8 months ago
Faster, parametric trajectory-based macromodels via localized linear reductions
— Trajectory-based methods offer an attractive methodology for automated, on-demand generation of macromodels for custom circuits. These models are generated by sampling the stat...
Saurabh K. Tiwary, Rob A. Rutenbar