2286 search results - page 3 / 458 » Statistical timing analysis based on a timing yield model |
ASPDAC
2005
ACM
14 years 11 months ago
2005
ACM
81
Voted
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
With aggressive scaling down of feature sizes in VLSI fabrication, process variation has become a critical issue in designs. We show that two necessary conditions for the "Ma...
74
Voted
ICCAD
2008
IEEE
15 years 6 months ago
2008
IEEE
Abstract— This paper presents an allocation method of decoupling capacitance that explicitly considers timing. We have found and focused that decap does not necessarily improve a...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing an...
79
Voted
PATMOS
2007
Springer
15 years 3 months ago
2007
Springer
Abstract. The continuous miniaturization of semiconductor devices imposes serious threats to design robustness against process variations and environmental fluctuations. Modern ci...