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FPL
2009
Springer
172views Hardware» more  FPL 2009»
15 years 2 months ago
Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
Nachiket Kapre, André DeHon
PPOPP
2009
ACM
15 years 4 months ago
NePalTM: design and implementation of nested parallelism for transactional memory systems
Abstract. Transactional memory (TM) promises to simplify construction of parallel applications by allowing programmers to reason about interactions between concurrently executing c...
Haris Volos, Adam Welc, Ali-Reza Adl-Tabatabai, Ta...
JPDC
2008
167views more  JPDC 2008»
14 years 9 months ago
A performance study of general-purpose applications on graphics processors using CUDA
Graphics processors (GPUs) provide a vast number of simple, data-parallel, deeply multithreaded cores and high memory bandwidths. GPU architectures are becoming increasingly progr...
Shuai Che, Michael Boyer, Jiayuan Meng, David Tarj...
IEEEPACT
2007
IEEE
15 years 4 months ago
The OpenTM Transactional Application Programming Interface
Transactional Memory (TM) simplifies parallel programming by supporting atomic and isolated execution of user-identified tasks. To date, TM programming has required the use of l...
Woongki Baek, Chi Cao Minh, Martin Trautmann, Chri...
PPOPP
2006
ACM
15 years 3 months ago
Optimizing irregular shared-memory applications for distributed-memory systems
In prior work, we have proposed techniques to extend the ease of shared-memory parallel programming to distributed-memory platforms by automatic translation of OpenMP programs to ...
Ayon Basumallik, Rudolf Eigenmann