Sciweavers

210 search results - page 34 / 42
» Switch Architectures For Small-buffered Optical Packet Switc...
Sort
View
83
Voted
ANCS
2006
ACM
15 years 1 months ago
Efficient memory utilization on network processors for deep packet inspection
Deep Packet Inspection (DPI) refers to examining both packet header and payload to look for predefined patterns, which is essential for network security, intrusion detection and c...
Piti Piyachon, Yan Luo
ANCS
2007
ACM
15 years 1 months ago
Experimenting with buffer sizes in routers
Recent theoretical results in buffer sizing research suggest that core Internet routers can achieve high link utilization, if they are capable of storing only a handful of packets...
Neda Beheshti, Jad Naous, Yashar Ganjali, Nick McK...
AHS
2006
IEEE
152views Hardware» more  AHS 2006»
15 years 3 months ago
Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
Balal Ahmad, Ahmet T. Erdogan, Sami Khawam
ANCS
2010
ACM
14 years 7 months ago
Axon: a flexible substrate for source-routed ethernet
This paper introduces the Axon, an Ethernet-compatible device for creating large-scale datacenter networks. Axons are inexpensive, practical devices that are demonstrated using pr...
Jeffrey Shafer, Brent Stephens, Michael Foss, Scot...
ADT
2011
14 years 1 months ago
Virtual networks: isolation, performance, and trends
Currently, there is a strong effort of the research community in rethinking the Internet architecture to cope with its current limitations and support new requirements. Many resea...
Natalia Castro Fernandes, Marcelo D. D. Moreira, I...