199 search results - page 7 / 40 » Switching Activity Minimization in Combinational Logic Desig... |
DAC
1996
ACM
15 years 3 months ago
1996
ACM
We propose a low-overhead scan design methodology which employs a new test point insertion technique to establish scan paths through the functional logic. The technique re-uses th...
FPGA
2007
ACM
15 years 5 months ago
2007
ACM
This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable...
INTEGRATION
2008
14 years 11 months ago
2008
In this paper an efficient algorithm for the synthesis and exact minimization of ESCT(Exclusive or Sum of Complex Terms) expressions for Boolean functions of at most six variables...
DAC
2006
ACM
16 years 17 days ago
2006
ACM
This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inve...
DAC
2005
ACM
15 years 1 months ago
2005
ACM
This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers ...