58 search results - page 11 / 12 » Synchronization and Communication in the T3E Multiprocessor |
IPPS
1994
IEEE
13 years 10 months ago
1994
IEEE
Present-day parallel computers often face the problems of large software Overheadsfor process switching and interprocessor communication. These problems are addressed by the Multi...
ERSA
2006
13 years 7 months ago
2006
In this paper we first outline and discuss the issues of currently accepted computational models for hybrid CPU/FPGA systems. Then, we discuss the need for researchers to develop ...
CODES
2009
IEEE
13 years 10 months ago
2009
IEEE
Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a softwarelike ...
GLVLSI
2006
IEEE
14 years 12 days ago
2006
IEEE
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
CODES
2009
IEEE
13 years 11 months ago
2009
IEEE
In a multiprocessor system-on-chip (MPSoC) private caches introduce the cache coherence problem. Here, we target at heterogeneous MPSoCs with a network-on-chip (NoC). Existing har...