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IOLTS
2005
IEEE
141views Hardware» more  IOLTS 2005»
15 years 5 months ago
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...
Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy
55
Voted
DAC
2004
ACM
15 years 5 months ago
A timing-driven module-based chip design flow
A Module-Rased design flow for digital ICs with hard and sofl modules is presented. Versions of the sofl modules are implemented with different areddelay characteristics. The vers...
Fan Mo, Robert K. Brayton
ASPDAC
2005
ACM
92views Hardware» more  ASPDAC 2005»
15 years 1 months ago
An LP-based methodology for improved timing-driven placement
— A method for timing driven placement is presented. The core of the approach is optimal timing-driven relaxed placement based on a linear programming (LP) formulation. The formu...
Qingzhou (Ben) Wang, John Lillis, Shubhankar Sanya...
DAC
2008
ACM
15 years 1 months ago
Analog parallelism in ring-based VCOs
The performance advantages in parallel ring-based VCOs are explored. When the number of VCOs is doubled, the parallel VCOs enhance phase noise by 3dB, and the within-chip process-...
Daeik D. Kim, Choongyeun Cho, Jonghae Kim
ET
2007
61views more  ET 2007»
14 years 11 months ago
Reliability and Defect Tolerance in Metallic Quantum-dot Cellular Automata
The computational paradigm known as quantum-dot cellular automata (QCA) encodes binary information in the charge configuration of Coulomb-coupled quantum-dot cells. Functioning QC...
Mo Liu, Craig S. Lent