61 search results - page 10 / 13 » Synthesis of Selectively Clocked Skewed Logic Circuits |
ET
2002
14 years 9 months ago
2002
In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our te...
ITC
1995
IEEE
15 years 1 months ago
1995
IEEE
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
111
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EH
2000
IEEE
15 years 1 months ago
2000
IEEE
Evolvable Hardware (EHW) refers to HW design and selfreconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, describing ...
VLSID
2009
IEEE
15 years 10 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
104
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CODES
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...