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» Synthesis of Selectively Clocked Skewed Logic Circuits
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GLVLSI
2006
IEEE
152views VLSI» more  GLVLSI 2006»
15 years 7 months ago
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
Rashed Zafar Bhatti, Monty Denneau, Jeff Draper
DAC
2000
ACM
16 years 2 months ago
Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization
In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of mult...
Hisaaki Katagiri, Keiichi Yasumoto, Akira Kitajima...
ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
15 years 10 months ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
DAC
2007
ACM
16 years 2 months ago
Global Critical Path: A Tool for System-Level Timing Analysis
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea...
LCN
2003
IEEE
15 years 6 months ago
An Optoelectronic Multi-Terabit CMOS Switch Core for Local Area Networks
Optoelectronic integrated circuits can support thousands of integrated optical laser diodes and photodetectors bonded to a high-performance CMOS substrate, and can be used in the ...
Honglin Wu, Amir Gourgy, Ted H. Szymanski