10159 search results - page 276 / 2032 » System Design Validation Using Formal Models |
124
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EURODAC
1995
IEEE
15 years 7 months ago
1995
IEEE
In order to extract a suitable common core information model, design representations on both system and architecture levels are analyzed. Following the specification trajectory, ...
121
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SIMUTOOLS
2008
15 years 4 months ago
2008
Model checking is a suitable formal technique to analyze parallel programs' execution in an industrial context because automated tools can be designed and operated with very ...
230
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FDL
2004
IEEE
15 years 7 months ago
2004
IEEE
gn process of embedded systems moves currently towards higher levels of abstraction. As a consequence, a need arises for an early and realistic assessment of system level design d...
136
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ICCAD
2009
IEEE
15 years 1 months ago
2009
IEEE
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
242
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TASE
2012
IEEE
13 years 11 months ago
2012
IEEE
— This paper presents new results on the formal design of distributed coordinating agents in a discrete-event framework. In this framework, agents are modeled to be individually ...