Sciweavers

4887 search results - page 668 / 978
» System Level Design Using C
Sort
View
DAC
2004
ACM
16 years 5 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
124
Voted
SAMOS
2004
Springer
15 years 10 months ago
with Wide Functional Units
— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...
Miquel Pericàs, Eduard Ayguadé, Javi...
HPCA
2008
IEEE
16 years 4 months ago
Supporting highly-decoupled thread-level redundancy for parallel programs
The continued scaling of device dimensions and the operating voltage reduces the critical charge and thus natural noise tolerance level of transistors. As a result, circuits can p...
M. Wasiur Rashid, Michael C. Huang
CHI
2006
ACM
16 years 4 months ago
Fast, flexible filtering with phlat
Systems for fast search of personal information are rapidly becoming ubiquitous. Such systems promise to dramatically improve personal information management, yet most are modeled...
Edward Cutrell, Daniel C. Robbins, Susan T. Dumais...
224
Voted
IPSN
2011
Springer
14 years 8 months ago
Duty-cycling buildings aggressively: The next frontier in HVAC control
Buildings are known to be the largest consumers of electricity in the United States, and often times the dominant energy consumer is the HVAC system. Despite this fact, in most bu...
Yuvraj Agarwal, Bharathan Balaji, Seemanta Dutta, ...